- Check for proper PG Connectivity.
Checking if Pins are logically connected to nets.
- Proper Legalization of Cells in Design.
No Cell overlap in the design. A legalized location is available for every cell.
- Congestion check for lower Cell/Pin density.
If still congestion persists, follow congestion reduction techniques like Cell Padding, Placement Blockages.
- Timing Check(Setup).
Setup violation is generally due to timing violation paths of higher delays. Making sure that max_cap, max_tran, and max_fanout are in control so that they wouldn’t violating the setup timing.
Reason for Setup Violation
When the data path gets delayed at the launch site of the flip-flop then it results in the setup violation. This can be due to poor transition of signal, lower drive strength.
- Signal transition can be improved by placing a back-to-back inverter in place of a buffer in a particular violation path. So that the transition is not too relaxed as in the previous case.
- Drive strength can be improved by increasing the drive strength of a cell by re-sizing it. Example: Converting the 2X Drive Strength to 4X. This reduces the Cell Delay, by eventually improving the timing.
What if still Setup gets Violated?
Creating Placement Bounds would help to mitigate Setup Violation.
Placement Bounds:
A Constraint that controls the group of hierarchical cells and leaf cells in design by reducing the net length. This helps to place cells at the most appropriate locations.
Most of the industries use this technique but have many scenarios to be considered.
Types of Bounds:
Soft Bounds: No guarantee that cells will be placed inside the bounds.
Hard Bounds: Forces placement of cells inside the bounds.
Exclusive Move Bounds: Certain specified cells are placed in the bounds and others must be placed outside.
icc_shell> create_bounds
Various syntax of create_bounds command:
[name bound_name]
[-coordinate {llx1 lly1 urx1 ury1 …}]
[-dimension {width height}]
[-effort low | medium | high | ultra]
[-type soft | hard ]
[-exclusive]
[-color range_0_to_63]
[-cycle_color]
object_list
5. Check for don’t use cells in design (Should be Zero).
