Swati Upadhyay

Author of STA Blogs| Physical Design Engineer

Introduction to Static Timing Analysis “STATIC” in STA STATIC refers to something independent w.r.t time in performing Timing Analysis. In Timing Analysis if you make the Analysis independent of the Input Vectors Applied (which is the only thing that can vary with time) then it is known as Static Timing Analysis. Now the question may arise that How it is...

Stages of STA Input and Output files in STA tool SDF (Standard Delay Format) SDF file is used for Fetching and Analyzing the timing data at any stage of the design process. The data in SDF file is in ASCII format and it is independent of the tool being used. It contains the below Design related information :-...

Setup Hold Time In previous blogs, you must be wondering what is the concept of Setup time and Hold time. So, now you will get a good understanding of the terms. Before proceeding to the Setup and Hold Time you should have an idea about the following terms:- Launch Flop The Flip-Flop that launches/sends the Data Signal is...

Timing Arcs and Unateness Timing Arc is defined as the path traversed by a Signal from the Input Pin of a Cell to its Output Pin. For a Cell, there can be more than one Timing Arc and by the information of different Timing Arcs that exists for a Cell, we can calculate the delay for each path that...

Propogation Delay When a signal is applied at the input pin of a logic gate then the output doesn’t change instantly. It will take some time to reflect the effect of change from the input Signal to the output, this is termed as “Propagation Delay” or Propagation Delay is defined as the difference between 50% change in...

Setup Hold Time Equation There are Setup and Hold checks in a design that ensures the data launched from the Launch Flop is captured correctly at the Capture Flop. The data launched at the Current Active Edge of the clock should be captured at the next Active Edge of the Clock. For this, the data should arrive at Setup...

How setup and hold time arises From Setup and Hold time Equation blog, you get a clear understanding of Setup Time and Hold Time. Now, the question that can arise is that from where this Setup Time and Hold Time concept arises. Every Flip Flop has its Setup requirement and Hold requirement for the proper Launch and Capture of Data. So...

Timing Paths When a Signal travels from its Start Point to its End Point the path traversed by the Signal is known as the Timing Path. To perform timing analysis the complete circuit is divided into different Timing Paths and then the delay is calculated. The Setup and Hold requirements of each Timing Path are calculated and...

Liberty File Liberty file contains Timing related information of all the Standard Cells and Macros in the Design. Timing information is presently based on a few PVT conditions. Every PVT Corner tested gives different Timing information. So, there is a different Liberty File for each PVT Corner. Liberty Files are generated by two types of models, namely...

Maximum Clock Frequency Consider the below circuit. In this circuit, every delay has two values i.e. minimum and maximum. A combinational circuit is present in the clock path. All the delays are in nanoseconds. Let us calculate the maximum and minimum clock path and data path delays: Maximum Data Path Delay = 3 + 12 + 3 +...

Clock Skew Skew is defined as the difference between the Arrival Time of the Clock Signal at the Clock pin of the Capture Flop and the Launch Flop. (Arrival Time at Capture Flop Pin – Arrival Time at Launch Flop Pin) Based on the above expression Skew can be...

Clock Jitter In a Circuit, there is a clock generating source either its PLL or a Clock Oscillator, or any other source. These Clock sources should maintain regular clock cycles with clean edges for the proper functioning of the Circuit. But, due to some issues for example Voltage Instability, Thermal Noise, Crosstalk, etc. the Clock Source is...

Clock Uncertainity Clock Uncertainty is used to model various factors like Skew, Jitter, Crosstalk, IR Drop, etc that can affect the Arrival of Clock Edge. By specifying Clock Uncertainty we get a window for Clock Edge, In that specified window Clock Edge can come at any point. Factors for Clock Uncertainty Pre CTS(Clock Tree Synthesis) : Ideal...

Clock Latency In every Circuit, there is a Clock Source and Clock Sinks. As every Flop is activated by a Clock Signal so Flops are the Sinks for Clock Signal. However, the Clock Signal takes some time to travel from its Source Point to the Sink Point. In short “Latency is defined as the time taken by...

Net Parasites Net Delay The difference in time taken by a signal when it is applied at one end of a net and reaches the other components connected to another end of the net is referred to as Net Delay. Net Delay is present due to the resistance and capacitance of the net and it is also...

Interconnect Delay Models Mainly the delay of a circuit can be put into two types of Delay i.e. Net Delay and Cell Delay. Net is defined as the wire connecting the Output Port of one Standard Cell or Block to the Input Port of another Standard Cell or Block. Note that a Net has only one Driver Cell/Block,...

Generated Clock and Virtual Clock Generated Clock When a clock is derived from a master clock it is referred to as a generated clock. The master clock is a clock defined by using the create_clock command. For example, if the generated clock is divided by 4 of the master clock, then the generated clock is defined in the output of...

Multicycle Path Generally, the Data Launched from Launch Flop takes a Single Clock Cycle to reach the Capture Flop. But, there are some cases when the Data is not able to travel from Launch to Capture Flop in Single Clock Cycle. So, in short, When the Data takes more than One Clock Cycle to travel from Launch...

Halfcycle Path The Launch Edge and the Capture Edge are either Positive or Negative and it is known as Single Cycle-Path. But, there are scenarios when Data is Launched at Positive Edge and Captured at Negative Edge and vice versa such cases form a Half Cycle-Path. In other words, when Setup Checks occur at Half Cycle it...

False Path In Static Timing Analysis, every Timing Path is checked for Setup and Hold Analysis to get an Optimized Design in terms of Timing and meeting the Timing Constraints. But, some Timing Paths need not be Optimized for Timing and STA does not perform Timing Analysis for those Paths. Such Paths are referred to as False...

Feed Through Path For a complete SoC design, the entire SoC is further divided into Blocks that have a particular functionality, and those functionalities are already defined. These blocks are interconnected to each other on the SoC. But, there can be some scenarios when the interacting blocks cannot be placed close to each other, then to connect them...

Clock Gating Multiple Clocks When there are many clocks present in a design then they must be having different waveforms and frequencies. So, such clocks are referred to as multiple clocks, and the logic triggered by each clock is called clock domain. When clocks have different frequencies then they repeat over a common base period. Asynchronous Clocks...

Website for learning and reference for all the subjects in VLSI Domain along with job assistance.

Website for learning and reference for all the subjects in VLSI Domain along with job assistance.

Website for learning and reference for all the subjects in VLSI Domain along with job assistance.

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