Introduction to Static Timing Analysis

Stages of STA

Setup Hold Time

Timing Arcs and Unateness

Propogation Delay

Setup Hold Time Equation

How setup and hold time arises

Timing Paths

Liberty File

Maximum Clock Frequency

Clock Skew

Clock Jitter

Clock Uncertainity

Clock Latency

Net Parasites

Interconnect Delay Models

Generated Clock and Virtual Clock

Multicycle Path

Halfcycle Path

False Path

Feed Through Path

Clock Gating