The development of the IEEE standard System Verilog language is described in this blog.

It illustrates how the language subsets System Verilog for Design and Verification, System Verilog Assertions, and System Verilog Functional Coverage fold into a single unifed language.

Introduction

Accellera introduced System Verilog in 2002. It became an IEEE standard in 2005. Later, in 2009, this standard was integrated with the Verilog standard and standardised as IEEE 1800-2009.

System Verilog is an upgraded version of Verilog that incorporates several verification features from Open Vera.

The biggest difference between System Verilog and other systems is that it is based on the notion of OOPs (object-oriented programming). System Verilog combines numerous verification features, such as functional coverage and assertions, into a single language.

Many businesses have used System Verilog as a verification medium.

Under a single simulation kernel, the System Verilog language contains four separate languages. They are as follows:

1. System Verilog for Design (synthesizable subset)
2. System Verilog for Verifcation (which includes the OOP subset)
3. System Verilog Assertions
4. System Verilog Functional Coverage

System Verilog for Design and Verification, System Verilog Assertions (SVA), and System Verilog Functional Coverage subsets are orthogonal.

Different features have their own syntax, but they all share a set of data types, expression operators, and so on. And all of these subsets operate under a single simulation kernel (simulation time tick).

Evolution of System Verilog Language

Every year, System Verilog is updated with new functionality, so let’s go over some of the points that are updated each year.

1. Around 1985, the Verilog language was introduced as the first generation of hardware design and verification languages. In 1995, it became an IEEE standard.

Note that designs in the late 1980s ranged from 10 to 100,000 gates; range and verification required a significant amount of gate-level verification as well as some RTL level. So, at the time, the language had sufficient functionality to deal with both design and verification.

2. The Verilog-2001 was a major upgrade to the standard that provided capabilities like multi-dimensional arrays, auto variables, and so on. Higher-level design constructs were added.

3. System Verilog 3.0 was available in early June of 2002. It introduced new sophisticated Verilog and “C” data types.

It was a significant step toward developing a comprehensive language for both design and verification. It extended Verilog’s synthesizable structures and permitted modelling hardware at higher levels of abstraction.

4. When System Verilog 3.1 became available in almost May of 2003, The language subset for verification was extensively rewritten in this edition.

It adds a “class” construct in the C++ manner, complete with methods, properties, inheritance, and so on. It also included facilities for confined random verification.

It also included the System Verilog Assertions (SVA) subset, which has improved semantics for sequential temporal domain expressions, sequence and property generation, and so on.

The Functional Coverage subset was also added to the language. It enables objectively measuring the functional coverage of a design using coverpoints, covergroups, bins, and so on.

5. Again, System Verilog 3.1a was available in May of 2004. Accellera proceeded to improve the System Verilog 3.1 standard by collaborating with key electronic design automation (EDA) businesses to verify that the System Verilog specification could be implemented correctly.

A few more modelling and verification constructs have also been defined. Accellera released System Verilog 3.1a, the final Accellera System Verilog version, in May 2004.

Accellera collaborated with the IEEE to create a new standards request in order to examine and standardise the System Verilog additions to Verilog. System Verilog was granted project number 1800 by IEEE, hence it is an IEEE 1800 standard.

6. Then came the 2012 version of the System Verilog standard. Then there’s System Verilog-2017.

Assertion

System Verilog IEEE 1800 includes various enhancements for large-scale design verification, using elements from the SUPERLOG, Vera, C, C++, and VHDL languages. System Verilog’s key technological donations include:

1. The SUPERLOG Extended Synthesizable Subset (SUPERLOG ESS)
2. PSL Assertions
3. OpenVera Assertions
4. Synopsys’ DirectC and coverage APIs
5. Bluespec’s tagged unions and high-level language features

Automated Testbench

To validate the complicated design, an automated testbench is necessary, which can compare the output from the DUT to some reference output. This testbench is essential since manual output comparison is not viable for complicated designs.

There are several components in the testbench, are as follow:

1. Transaction: This is an abstraction of all the signals found in DUT.
2. Generator: This component creates various input stimuli for the DUT.
3. Driver: This component is responsible for driving the different signals based on the stimulus given by the generator.
4. Monitor: This component watches the i/p and o/p signals and samples them when an event occurs. The reference output is compared to the sampled signal.
5. Scoreboard: This component is in charge of comparing the sampled packet to the reference packet.
6. Environment: This incorporates all of the test bench’s components into a single entity.

Difference between Verilog and System Verilog

Let’s see how the System Verilog is different from Verilog.

Verilog is mostly used to create RTL codes, whereas System Verilog was created to make creating test benches easier, but it may also be used to write RTL.

In Verilog, there are four event regions, whereas System Verilog has nine.

In Verilog, all data types are of the 4-state type, whereas in System Verilog introduced new data types to hold 2 state values.

Verilog is not based on the concept of OOPS, but System Verilog is based on the concept of OOPs.

There have been several additions to System Verilog that are difficult to list in a single blog. In subsequent articles, we will look in depth at the changes made in System Verilog.

So for this blog, let’s summarise it with a few questions.

1. What do you mean by System Verilog?
2. How has System Verilog evolved?
3. What are the assertions in System Verilog?
4. Describe the various components of the testbench.
5. How does System Verilog differ from Verilog?