Procedural Assignment
In our previous blog, we talked about the procedural assignment in Verilog. These are almost the same in System Verilog, so let’s discuss that in this blog. Procedural assignments come in the form of procedural blocks like “always”, “initial,” “task,” and “function.” To regulate when assignments are assessed and/or assigned, event controls, delay controls, if…else…
Arrays
We earlier studied the data types of System Verilog, but now we will study arrays of System Verilog, which is also a basic foundation of it. This blog introduces the language’s arrays. Packed, unpacked, associative, and dynamic arrays are specifically explored. There is discussion of array assignment, indexing, slicing, array manipulation methods, and array ordering…
Data Type, Typedef methods
Data Type In the previous blog we already introduced System Verilog, so let’s start this with some more interesting basic terms, i.e., data types. SystemVerilog provides a wide range of integer and real data types, as well as nets. Verilog used to have “reg” and “wire,” but they were insufficient for functional verification. SystemVerilog additionally…
System Verilog
The development of the IEEE standard System Verilog language is described in this blog. It illustrates how the language subsets System Verilog for Design and Verification, System Verilog Assertions, and System Verilog Functional Coverage fold into a single unifed language. Introduction Accellera introduced System Verilog in 2002. It became an IEEE standard in 2005. Later,…
LED Interfacing with FPGA
From the previous blog, we already know about FPGA, like how it works, its structure, and its type. It means we already know the basic things about FPGA but let’s know some more facts about FPGA. FPGA Program FPGA programming uses an HDL to alter circuits based on the capabilities desired for the device. Because…
Introduction to FPGA & CPLD
In this blog, we will look at a subtopic known as Field Programmable Gate Arrays, or simply FPGA and CPLD. We will discuss the principle of Programmable Logic Devices (PLD) and several of their types. We will also look at the architecture of a typical FPGA device and CPLD and its benefits. Introduction FPGAs are…
MISR (Multiple input signature register)
In this blog, we will learn how to design MISR, or Multiple Input Signature Register, in Verilog, but first, we should understand what MISR is. So, let’s start a blog in a fresh and exciting way. In working in individual test (BIST) strategies, putting away all the circuit yields on a chip isn’t feasible, but…
Shift Unit Design
In today’s blog, we will learn to design a shift unit. But, because jumping right into the design process will not be interesting, let’s start with some shift unit basic knowledge. Arithmetic Logic Shift Unit The Arithmetic Logic Shift Unit (ALSU) is a component of a computer system’s Arithmetic Logic Unit (ALU). It is a…
Traffic Light Controller
This is an interesting blog and somehow unique as well, so we will discuss it now. We know about the traffic light controller,but let’s start with the beginning. The primary function of traffic control signals is to assign right-of-way at intersections where a continuous flow of cars on one lane would cause significant delay for…
Flipflops
We have studied lots of things related to Verilog, so let’s learn to design something new through Verilog. A flip-flop or latch is a bistable multivibrator that has two stable states and may be used to store state information. Signals provided to one or more control inputs can cause the circuit to change state, and…
