Consider the below circuit. In this circuit, every delay has two values i.e. minimum and maximum. A combinational circuit is present in the clock path. All the delays are in nanoseconds.
Fig. 1: Clock Path and Data path Delay
Let us calculate the maximum and minimum clock path and data path delays:
- Maximum Data Path Delay = 3 + 12 + 3 + 10 + 3 = 31ns
- Minimum Data Path Delay = 2 + 10 +2 + 7 + 2 = 23ns
- Maximum Clock Path Delay = 4 + 10 + 4 = 18ns
- Minimum Clock Path Delay = 3 + 6 + 3 = 12ns
To find a minimum clock period we must ensure that at capture flop i.e. FF2 in this example the data must be present setup time before the positive clock edge.
The data can take a minimum of 23ns and a maximum of 31ns concerning the original clock edge and the Clock can take a minimum of 12ns and a maximum of 18ns to reach Capture flop FF2 concerning the original clock edge.
Now, the clock period considering all 4 combinations are:
- T1= Max Data Path Delay – Max Clock Path Delay + Tsetup = 31 – 18 + 5 = 18 ns
- T2 = Min Data Path Delay – Min Clock Path Delay + Tsetup = 23 – 12 + 5 = 16 ns
- T3 = Max Data Path Delay – Min Clock Path Delay + Tsetup = 31 – 12 + 5 = 24 ns
- T4 = Min Data Path Delay – Max Clock Path Delay + Tsetup = 23 – 18 + 5 = 10 ns
It can be observe that the minimum clock period must be T3 i.e. 24 ns or greater that 24 ns for the proper functioning of the circuit. If Clock period is less than 24 ns then the one or all of the scenarios will fail.
Minimum Clock Period = (Maximum Data Path Delay – Minimum Clock Path Delay) + Tsetup
Maximum Operating Frequency = (1/Minimum Clock Period)
