Timing Control

In our last blog, we studied different types of statements. Let’s discuss today the another part.

Verilog provides a number of behavioural timing control mechanisms. The simulation time in Verilog does not advance if there are no timing control statements.

Timing settings allow you to select the simulation time when procedural statements will be executed.

Timing control may be done in three ways: delay-based timing control, event-based timing control, and level-sensitive timing control.

Delay-based Timing Control

In the earlier blogs, we utilised delay-based timing control statements but did not describe them in depth.

In an expression, delay-based timing control provides the time interval between when the statement is encountered and when it is performed.

We’ll talk about delay-based timing control statements in this section. This # symbol represents delays. The delay-based timing control statement’s syntax is presented below.


: := #<NUMBER>

| | = #<identifier>

| | = #(<mintypmax_expression> <,<mintypmax_expression>>*)

A number, an identifier, or a mintypmax expression can be used to specify delay-based timing control.

For procedural assignments, there are three forms of delay control: normal delay control, intra-assignment delay control, and zero delay control.

Inter delay control

When a non-zero delay is supplied to the left of a procedural assignment, inter delay control is employed.

Intra-assignment delay

When a delay can be specified to the right of the assignment operator, This type of delay specification changes the flow of activities in a different way.

reg a, b, c;					// define register value
initial						//intra assignment delay
    a=0; c=0;
b = #5 a + c;

initial						//with inter assignment delay
    a=0; c=0;
    temp_ac = x+z;
    #5 b=temp_ac

Take note of the distinction between intra-assignment and inter delays from above examples. Inter delays postpone the completion of the entire task.

Intra-assignment delays compute the right-side expression at the present time and postpone the assignment of the computed value to the left-side variable.

Intra-assignment delays are analogous to utilising inter-assignment delays in conjunction with a temporary variable to hold the current value of a right-hand-side expression.

Zero delay control

At the same simulation time, procedural statements in distinct always-initial blocks may be examined. The sequence in which these statements are executed in separate always-initial blocks is nondeterministic.

Zero delay control is a technique for ensuring that a statement is performed after all other statements in that simulation time have been executed.

Event-based Timing Control

A change in the value of a register or a net is referred to as an event. Events can be used to initiate the execution of a statement or a set of statements. Event-based timing control is classified into four categories. Regular event control, named event control, event OR control, and level-sensitive timing control are all types of event control.

Regular event control

Statements can be executed when the signal value changes or when the signal value transitions from positive to negative. The “#” symbol represents an event control.

Named event control

You can specify an event, then trigger and identify its occurrence. The event has no data. The keyword event declares a specified event.

The ” ->” symbol causes an event to occur. The event’s triggering is indicated by the sign “@”.

Event OR control

A transition on any of several signals or events can sometimes cause the execution of a statement or a block of statements.

This is stated as an OR of event or signals. A sensitivity list is a set of events or signals expressed as an OR.


Level-sensitive timing control

The earlier described event control waited for a change in a signal value or the triggering of an event. Edge-sensitive control was given by the symbol.

Verilog also supports level-sensitive timing control, which allows you to wait for a condition to be true before executing a statement or a block of statements. For level-sensitive constructions, the keyword “wait” is used.

The value of count_enable is continually noted in the example.

  wait (count_enable) #20 count = count + 1;

If count_enable is zero, the statement is skipped. If it is logical 1, the expression count = count + 1 is performed 20 time units later. If count enabled is set to 1, the count will be increased every 20 units.

So, after reading this blog today, we learnt about timing controls and their many sorts. To summarise this blog, here are some questions you may simply answer.

  1. What is timing control and what are its many types?
  2. What exactly is delay-based timing control, and how many different forms of delay-based timing control exist?
  3. What is the distinction between normal and intra-assignment delay?
  4. What is event-based timing control and what are its many types?
  5. What precisely is level-sensitive timing control?
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